The reason modern chips stall isn't the transistors

Here's the deal: Samsung Electronics and the Gwangju Institute of Science and Technology (GIST) announced jointly on August 21 that they achieved a world-first technique cutting the resistance of ultra-fine metal interconnects by roughly 45%. The underlying paper appeared in Science on August 13.

Semiconductor news is usually about transistors — 3nm, 2nm, gate-all-around. But what actually throttles chip performance today isn't the transistor. It's the wires between transistors.

A chip holds billions of transistors, connected by dozens of stacked layers of metal wiring. As circuits shrink, those wires shrink too. Thinner wire, higher resistance. Higher resistance means slower signal propagation, more heat, more power draw. However fast you make the transistor, the chip is slow if the wiring can't keep up.

The industry calls this RC delay — R for resistance, C for capacitance. Deeper into the scaling curve, the time a signal spends traveling the wires dominates the time a transistor spends switching. A large share of why AI accelerators and HPC chips struggle on power efficiency lives right here.

The cast — copper's ceiling, and ruthenium

Copper has been the wiring material for decades, standard since IBM moved from aluminum in the late 1990s. It conducts well and is comparatively workable.

But copper degrades badly when it gets very thin. Two reasons.

First, electron scattering. Electrons move freely inside a metal, but as a wire narrows, collisions with surfaces and grain boundaries rise sharply. Once the conductor's dimensions approach the electron mean free path, you don't get bulk conductivity anymore. Copper suffers this acutely.

Second, barrier layers. Copper diffuses into surrounding dielectric, so it needs thin barrier and liner layers wrapped around it. When wires were thick, those layers were negligible. At single-digit-nanometer widths, the barrier consumes a substantial fraction of the wire's cross-section — the copper actually carrying current shrinks by exactly that much.

Which is why ruthenium became the leading alternative. Ruthenium has worse bulk conductivity than copper, yet performs better in very thin wires: its electron mean free path is short, so degradation with scaling is gentler, and critically, it needs essentially no diffusion barrier. No barrier means the full conductor cross-section is usable. Cobalt and molybdenum have been studied too, but ruthenium has drawn the most attention in recent years.

Ruthenium had its own problem, though. Deposited as a thin film with small, randomly oriented grains, electrons scatter continuously at grain boundaries. Swapping the material does not automatically lower resistance. The grains have to be large and their orientation aligned before the material's advantage shows up as performance.

It's worth unpacking why orientation matters. A metal film is an assembly of many small crystal grains. Electrons scatter where grains meet. Larger grains mean fewer boundaries, and aligned orientation weakens scattering at the boundaries that remain. Same material, same thickness, very different resistance depending on how the microstructure formed. Choosing the material is only half the problem; engineering its microstructure is the other half — and that's exactly where this result sits.

Surface states add another variable. At extreme thinness, electron behavior near the surface diverges from the bulk, and band-structure modulation itself has to be accounted for. Recent theoretical work on ultrathin ruthenium interconnects addresses precisely this. Answers here need experiment and calculation together, which is part of why university and institute collaboration is essential.

What Samsung did — carbon as a promoter

Samsung's SAIT research institute found the answer in trace amounts of carbon.

By introducing a small quantity of carbon during deposition, they induced recrystallization in the ruthenium film, controlling both grain size and crystal orientation. The result is a highly textured ruthenium film. The key detail: carbon isn't an ingredient that remains in the final film. It's a transient processing aid, and the target is the microstructure of the finished ruthenium.

The more notable technical point is that this doesn't rely on lattice-matched epitaxial growth. The conventional route to aligning crystal orientation is to grow the film in registry with the substrate's crystal structure — which constrains substrate choice and is awkward to put into volume manufacturing. Promoter-driven recrystallization escapes that constraint.

Item Detail
Result ~45% reduction in line resistance of ultra-fine interconnects
Baseline Identical ruthenium wiring without the carbon promoter
Method Trace carbon controlling ruthenium grain size and orientation
Publication Science (2026-08-13)
Authors 13 total — 11 from Samsung SAIT, plus GIST and MIT researchers
Announcement Samsung Electronics and GIST, jointly (2026-08-21)

Read the 45% against the right baseline. It is not versus copper. It's versus the same ruthenium wiring without the carbon promoter. So the claim isn't "switching to ruthenium cuts resistance 45%" — it's "when using ruthenium, this technique cuts resistance a further 45%." Easy to misread from a headline.

The author list tells you what kind of work this is. Eleven of thirteen authors are Samsung SAIT, with GIST and MIT participating. This isn't university-led basic research; it's a corporate lab leading, with academia contributing theory and analysis. Publication in Science means the novelty was recognized — and separately, that a long road to volume production remains.

There's precursor work, too. SAIT presented research on grain-orientation control in atomic-layer-deposited ruthenium at IEDM in November 2025. This Science paper extends that line, moving from a conference result to a top-tier journal.

"World-first" deserves precise reading as well. It doesn't mean nobody made ruthenium interconnects before — that research has run for years across many institutions, including consortium work at imec. What's first here is demonstrating this magnitude of resistance reduction via carbon-promoted recrystallization to align grain orientation. Corporate "world-first" claims are usually scoped to a specific method and condition, so it pays to identify which part is actually new.

What each side gets

For Samsung Foundry, this is roadmap material. Foundry competition isn't decided on transistor structure alone. At the same node, lower interconnect resistance lets you raise clock frequency or lower power. Wiring is as much a competitive axis against TSMC as transistor density, and leading there is a real card.

For AI chip designers, it's a power-budget question. Power and heat are the dominant constraints on data-center GPUs and accelerators — chips per rack, cooling cost, and the facility's total power contract all tie back to it. Lower interconnect resistance means the same performance at lower power, which means more compute inside the same power envelope.

For GIST and Korea's research ecosystem, it's a reference point. A domestic university producing Science-level results alongside a global corporate lab affects follow-on funding and recruiting directly, and MIT's participation signals working international collaboration channels.

For materials and equipment suppliers, it's new demand. Ruthenium precursors, deposition equipment, and process control for a carbon promoter require a different toolset from copper. If ruthenium interconnects enter production, supply chains and equipment markets reshuffle. Ruthenium is a platinum-group metal, though, with limited supply and volatile pricing.

For semiconductor talent in Korea, there's a signal too. Materials and process work has drawn less attention than design or software, but as scaling hits physical limits, its importance rises — precisely because changing transistor structure alone no longer delivers. Work like this landing in Science registers with researchers in the field.

Some parties gain nothing soon. For anyone buying chips, this takes time to reach product. Moving a research result into production means validating yield, reliability, long-term degradation, and compatibility with existing process flow. Paper to fab line typically runs in years.

Precedents — the history of interconnect material transitions

The big precedent is aluminum to copper. When IBM announced copper interconnects in 1997, the motivating problem rhymed with today's: as wires thinned, aluminum hit walls on resistance and electromigration. The transition succeeded, but becoming standard took years, because barrier-layer technology and the damascene process had to mature alongside it.

The lesson: you don't swap a material, you rebuild a process. Same for ruthenium. Deposition, etch, planarization, inspection — change the wiring material and everything around it is affected.

Cobalt interconnects are the half-case. Intel introduced cobalt in lower metal layers at its 10nm node and struggled in production versus theoretical expectation. Intel's 10nm delays had many causes, and cobalt interconnects are frequently listed among them. A great lab result can still collapse on production yield.

EUV lithography is the counterexample where patience paid. ASML took close to twenty years to bring EUV to commercial viability, with several rounds of public skepticism along the way, and it is now indispensable. The takeaway: treat semiconductor fundamental research as having a long gap between announcement and production.

Hybrid bonding and backside power delivery (BSPDN) attack the same problem structurally rather than materially, moving power-delivery wiring to the chip's back side to relieve congestion on signal wiring. Material improvement and structural innovation are advancing in parallel, and real chips will need both.

Memory may feel this too. Interconnect resistance isn't only a logic problem; DRAM and NAND face wordline and bitline resistance limits as cells shrink. Samsung builds both, so wiring technology developed on one side can migrate. Process structures and requirements differ enough that it won't transfer directly.

How competitors respond

TSMC has researched alternative interconnect materials including ruthenium for years. In foundry competition, this kind of fundamental work is partly public through conferences and papers, but adoption timing and conditions are trade secrets. Publishing in Science first doesn't establish a production lead.

Intel has claimed leadership in backside power delivery — attacking wiring congestion structurally. Whether material improvement or structural change delivers first is unsettled.

Consortia like imec matter a lot here. No single company can screen the full candidate space for interconnect materials, so consortium screening with results shared among members has become the norm. Ruthenium narrowing to front-runner status is itself a product of that model.

Chinese research groups are a variable too. With advanced lithography access restricted, Chinese institutions have concentrated on axes less dependent on tooling — materials, 3D stacking, packaging. Interconnect materials fit that strategy well, and papers on ruthenium and molybdenum wiring from Chinese groups have risen noticeably in recent years.

Equipment and materials firms stand to gain regardless of which material wins, but need lead time. Few companies can supply ruthenium precursors reliably, and platinum-group sourcing carries geopolitical exposure.

What actually changes for you

If you work in semiconductors, read this as interconnects rising to a headline competitive axis. Process competition has been narrated through transistor structure for years; expect wiring materials and backside power delivery to appear far more often in roadmap presentations.

If you run AI infrastructure, nothing changes today, but the direction is worth holding. Multiple paths to better per-chip power efficiency are advancing at once, and interconnect resistance is one. Extrapolating current-generation chip power characteristics across a multi-year data-center power contract will overestimate.

If you're a chip designer, lower resistance returns as design headroom. Today you compensate for wire delay with repeaters, wider wires and more layers — all of which cost area and power. Cutting resistance shrinks that compensation and fits more function in the same area. That applies once the process is available to you, not to designs in flight.

If you're an investor, there isn't much to act on. The gap between research and production is long, and Samsung hasn't said which node gets this or when. The thing to watch is whether ruthenium interconnects appear in Samsung Foundry's future process roadmap disclosures.

If you're in materials or equipment, the ruthenium supply chain deserves attention — constrained platinum-group supply, high barriers in precursor chemistry and deposition tooling. Demand appears abruptly once a material transition is confirmed, so timing preparation matters.

If you're a researcher or student, this is a useful model of industry-academia collaboration: a corporate lab leading, universities supplying theory and analysis, producing a top-journal result. It also illustrates how many problems in semiconductor materials are hard to attack from academia alone.

🥄 Three Things You're Probably Wondering

— Does 45% mean chips get 45% faster? No. It's the line resistance of a specific interconnect, measured against the same ruthenium wiring without the carbon promoter. Whole-chip performance depends on transistors, wiring, memory bandwidth and architecture together. Interconnect resistance is one axis, and the gain matters most for power efficiency.

— When does it reach real chips? No timeline has been published. Moving a paper result into a production process requires validating yield, reliability, long-term degradation and compatibility with existing flow, and typically takes years. Intel's cobalt interconnects went well in the lab and struggled in production, so a single announcement doesn't support a date.

— Is copper finished? Not for a while. Interconnects stack in dozens of layers of differing width. The realistic path uses alternative materials only in the thinnest lower layers while thicker upper layers stay copper. Material transitions happen layer by layer, not all at once.

Sources

Numbers and criteria are as of announcement and may change.